This invention relates generally to a method for the automated placement of cells in the generation of an automated layout of an integrated circuit, and more specifically to a method for the automated placement of cells in an integrated circuit layout that accommodates symmetry constraints that are often encountered in the layout of analog devices.
A number of techniques exist for the computer-aided design (CAD) and layout of integrated circuit devices. The integrated circuit device is first divided into a number of cells that can be used to implement the desired integrated circuit function. The cells can be, for example, an individual device, a capacitor, or, often, a plurality of transistors and other devices that make up a logic block. Most of the prior art techniques then involve the placement of the cells either in accordance with a trial and error method or in accordance with a mathematical algorithm. The known placement techniques usually handle the cells as rectangles and move and position the rectangular cells in such a manner to optimize the size of the integrated circuit layout.
Although the known automated layout techniques are not ideal, they are reasonably effective for providing a workable layout for digital circuits. Unfortunately, however, the known techniques are not practical or efficient for optimum layout of an analog integrated circuit. In addition to the obvious functional differences between analog and digital circuits, analog circuits differ from digital circuits in that an analog circuit layout often requires aspects of symmetry and device matching in order for the resulting integrated circuit to achieve optimum performance.
Known techniques for laying out integrated circuits are not efficient for laying out circuits requiring symmetry and matching. Dealing with symmetry and matching using the known automated layout techniques requires unacceptable amounts of computing time and/or computing power.
A need therefore existed for an improved method for the automated placement of cell in the generation of integrated circuit layouts, and especially for the automated placement of cells in the layout of analog circuits that require aspects of device symmetry and device matching.
In accordance with one embodiment of the invention, a method is provided for the automated packing of an integrated circuit layout, and especially for the automated packing of an integrated circuit layout within which certain cells of the circuit must be symmetrically arranged. In accordance with one embodiment of the invention, the circuit to be designed is considered as a plurality of generally rectangular cells. From the plurality of cells making up the integrated circuit, a subset of cells that must exhibit symmetry are identified. Symmetry constraints are defined for the subset of symmetric cells. The packing of the cells, in accordance with one embodiment of the invention, is encoded as ordered sequence-pairs starting with an initial sequence-pair that is symmetric-feasible. The encoding is then optimized using simulated annealing, with each movement of cells during the annealing subject to the symmetry constraints.